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description the hcpl-260l/060l/263l/063l are optically coupled gates that combine a gaasp light emitting diode and an integrated high gain photo detector. an enable in- put allows the detector to be strobed. the output of the detector ic is an open collector schottky-clamped transistor. the internal shield provides a guaranteed common mode transient immunity speci?cation of 15 kv/s at 3.3v. this unique design provides maximum ac and dc circuit isolation while achieving lvttl/lvcmos compati-bili- ty. the optocoupler ac and dc operational parameters are guaranteed from C40 c to +85 c allowing trouble- free system performance. these optocouplers are suitable for high speed logic interfacing, input/output bu?ering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments. functional diagram features 3.3v/5v dual supply voltages low power consumption 15 kv/s minimum common mode rejection (cmr) at v cm = 1000 v high speed: 15 mbd typical lvttl/lvcmos compatible low input current capability: 5 ma guaranteed ac and dc performance over tempera- ture: C40 c to +85 c available in 8-pin dip, soic-8 strobable output (single channel products only) safety approvals: ul, csa, iec/en/din en 60747-5-2 applications isolated line receiver computer-peripheral interfaces microprocessor system interfaces digital isolation for a/d, d/a conversion switching power supply instrument input/output isolation ground loop elimination pulse transformer replacement field buses hcpl-260l/060l/263l/063l high speed lvttl compatible 3.3 volt optocouplers data sheet lead (pb) free rohs 6 fully compliant r o h s 6 f u lly comp l ia n t optio n s a v ai l ab l e ; -xxxe de n otes a l ead -f ree product 1 2 3 4 8 7 6 5 cathode anode gnd v v cc o 1 2 3 4 8 7 6 5 anode 2 cathode 2 cathode 1 anode 1 gnd v v cc o2 v e v o1 hcpl-260l/060l hcpl-263l/063l nc nc led on off on off on off enable h h l l nc nc output l h h h l h truth table (positive logic) led on off output l h truth table (positive logic) shield shield a 0.1 f bypass capacitor must be connected between pins 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
2 ordering information hcpl-xxxx is ul recognized with 3750 vrms for 1 minute per ul1577 part number option package surface mount gull wing tape & reel ul 5000 vrms/ 1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-260l -000e no option 300mil dip-8 50 per tube -300e -300 x x 50 per tube -500e #500 x x x 1000 per reel -020e -020 x 50 per tube -320e -320 x x x 50 per tube -520e -520 x x x x 1000 per reel -060e #060 x 50 per tube -560e #560 x x x x 1000 per reel hcpl-263l -000e no option 300mil dip-8 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel -020e #020 x 50 per tube -320e -320 x x x 50 per tube -520e #520 x x x x 1000 per reel -060e -060 x 50 per tube -560e -560 x x x x 1000 per reel hcpl-060l -000e no option so-8 x 100 per tube -500e #500 x x 1500 per reel -060e #060 x x 100 per tube -560e -560 x x x 1500 per reel hcpl-063l -000e no option so-8 x 100 per tube -500e #500 x x 1500 per reel -060e -060 x x 100 per tube -560e -560 x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. combination of option 020 and option 060 is not available. example 1: hcpl-260l-560e to order product of 300mil dip gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: hcpl-263l to order product of 300mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
3 schematic shield 8 6 5 2+ 3 v f use of a 0.1 f bypass capacitor connected between pins 5 and 8 is recommended (see note 5). C i f i cc v cc v o gnd i o v e i e 7 hcpl-260l/060l shield 8 7 + 2 v f1 C i f1 i cc v cc v o1 i o1 1 shield 6 5 C 4 v f2 + i f2 v o2 gnd i o2 3 hcpl-263l/063l package outline drawings 8-pin dip package 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 option code* ul recognition ur type number * marking code letter for option numbers "v" = option 060 option number 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 3.56 0.13 (0.140 0.005)
4 8-pin dip package with gull wing surface mount in option 500 (hcpl-260l, hcpl-263l) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 C 0.051 (0.010 + 0.003 C 0.002) small outline so-8 package xxxv yww 8765 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
5 solder re?ow temperature pro?le 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering time 200 c preheating time 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/C0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/C0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. recommended pb-free ir pro?le 217 c ramp-down 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide ?ux should be used. note: non-halide ?ux should be used.
6 insulation and safety related speci?cations 8-pin dip (300 mil) so-8 parameter symbol value value units conditions minimum external air l (101) 7.1 4.9 mm measured from input terminals to output gap (external clearance) terminals, shortest distance through air. minimum external tracking l (102) 7.4 4.8 mm measured from input terminals to output (external creepage) terminals, shortest distance path along body. minimum internal plastic 0.08 0.08 mm through insulation distance, conductor gap (internal clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. tracking resistance cti 200 200 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1) regulatory information the hcpl-260l/060l/263l/063l have been approved by the following organizations: ul approval under ul 1577, component recognition program, file e55361. csa approval under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 (option 060 only)
7 iec/en/din en 60747-5-2 insulation related characteristics description symbol pdip option 060 so-8 option 060 units installation classi?cation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv for rated mains voltage 300 v rms i-iv i-iii for rated mains voltage 600 v rms i-iii i-ii climatic classi?cation 55/85/21 55/85/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 630 560 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test v pr 1181 1063 v peak with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, v pr 945 849 v peak t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage* v iotm 6000 4000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values (see below for thermal derating curve figures) case temperature t s 175 150 ?c input current i s,input 230 150 ma output power p s,output 600 600 mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 *refer to the front of the optocoupler section of the current catalog, under product safety regulations section iec/en/din en 6 0747-5-2, for a detailed description. note: isolation characteristics are guaranteed only within the safet y maximum ratings which must be ensured by protective circuits i n applica- tion. thermal derating curve figures output power C p s , input current C i s 0 0 t s C case temperature C c hcpl-060l/hcpl-063l 200 700 400 25 800 50 75 100 200 150 175 p s (mw) i s (ma) 125 100 300 600 500 output power C p s , input current C i s 0 0 t s C case temperature C c 200 700 400 25 800 50 75 100 200 150 175 p s (mw) i s (ma) 125 100 300 600 500 hcpl-260l/hcpl-263l
8 absolute maximum ratings (no derating required up to 85?c) parameter symbol package** min. max. units note storage temperature t s C55 125 ?c operating temperature? t a C40 85 ?c average forward input current i f single 8-pin dip 20 ma 2 single so-8 dual 8-pin dip 15 1, 3 dual so-8 reverse input voltage v r 8-pin dip, so-8 5 v 1 input power dissipation p i 40 mw supply voltage (1 minute maximum) v cc 7 v enable input voltage (not to exceed v e single 8-pin dip v cc + 0.5 v v cc by more than 500 mv) single so-8 enable input current i e 5 ma output collector current i o 50 ma 1 output collector voltage v o 7 v 1 output collector power dissipation p o single 8-pin dip 85 mw single so-8 dual 8-pin dip 60 1, 4 dual so-8 lead solder temperature t ls 8-pin dip 260?c for 10 sec., 1.6 mm below (through hole parts only) seating plane solder re?ow temperature pro?le so-8 see package outline drawings (surface mount parts only) section **ratings apply to all devices except otherwise noted in the package column. recommended operating conditions parameter symbol min. max. units input current, low level i fl * 0 250 a input current, high level [1] i fh ** 5 15 ma power supply voltage v cc 2.7 3.6 v 4.5 5.5 low level enable voltage v el 0 0.8 v high level enable voltage v eh 2.0 v cc v operating temperature t a C40 85 ?c fan out (at r l = 1 k) [1] n 5 ttl loads output pull-up resistor r l 330 4 k *the o? condition can also be guaranteed by ensuring that v fl 0.8 volts. **the initial switching threshold is 5 ma or less. it is recommended that 6.3 ma to 10 ma be used for best performance and to permit at least a 20% led degradation guardband.
9 electrical speci?cations over recommended operating conditions (t a = C40 c to +85 c , 2.7v v cc 3.6v) unless otherwise speci?ed. all typicals at v cc = 3.3 v, t a = 25 c. all enable test conditions apply to single channel products only. see note 5. parameter sym. device min. typ. max. units test conditions fig. note high level i oh * 4.5 50 a v cc = 3.3 v, v e = 2.0 v, 1 1, 15 output current v o = 3.3 v, i f = 250 a input threshold i th 3.0 5.0 ma v cc = 3.3 v, v e = 2.0 v, 2 15 current v o = 0.6 v, i ol (sinking) = 13 ma low level v ol * 0.35 0.6 v v cc = 3.3 v, v e = 2.0 v, 3 15 output voltage i f = 5 ma, i ol (sinking) = 13 ma high level i cch single 4.7 7.0 ma v e = 0.5 v i f = 0 ma supply current dual 6.9 10.0 v cc = 3.3 v low level i ccl single 7.0 10.0 ma v e = 0.5 v i f = 10 ma supply current dual 8.7 15.0 v cc = 3.3 v high level i eh single C0.5 C1.2 ma v cc = 3.3 v, v e = 2.0 v enable current low level i el * single C0.5 C1.2 ma v cc = 3.3 v, v e = 0.5 v enable current high level v eh single 2.0 v 15 enable voltage low level v el single 0.8 v enable voltage input forward v f 1.4 1.5 1.75* v t a = 25?c, i f = 10 ma 5 1 voltage input reverse bv r * 5 v i r = 10 a 1 breakdown voltage input diode ?v f / C1.6 mv?c i f = 10 ma 1 temperature ?t a coe?cient input c in 60 pf f = 1 mhz, v f = 0 v 1 capacitance *the jedec registration speci?es 0?c to +70?c. avago speci?es C40?c to +85?c.
10 electrical speci?cations (dc) over recommended operating conditions (t a = -40 c to +85 c, 4.5v v dd 5.5v) unless otherwise speci?ed. all typicals at v cc = 5 v, t a = 25 c. parameter symbol channel min. typ.* max. units test conditions fig. note high level output current i oh 5.5 100 av cc = 5.5 v, v o = 5.5 v, i fl = 250 a 1 1,15 input threshold current i th single 2.0 5.0 ma v cc = 5.5 v, v o = 0.6 v, i ol > 13 ma 2 15 dual 2.5 low level output voltage v ol 0.35 0.6 v v cc = 5.5 v, i f = 5 ma, i ol (sinking) = 13 ma 3 15 high level supply current i cch single 7.0 10.0 ma v e =0.5v, v cc = 5.5 v, i f = 0 ma 6.5 ma v e =v cc , v cc = 5.5 v, i f = 0 ma dual 10.0 15.0 v cc = 5.5 v, if = 0 ma low level supply current i ccl single 9.0 13.0 ma v e =0.5v, v cc = 5.5 v, i f = 0 ma 8.5 ma v e =v cc , vv = 5.5 v, if = 0 ma dual 13.0 21.0 ma v cc = 5.5 v, i f = 0 ma high level enable current i eh single -0.7 -1.6 ma v cc = 5.5 v, v e = 2.0v low level enable current i el single -0.9 -1.6 ma v cc = 5.5 v, v e = 0.5v high level enable voltage v eh single 2.0 v 15 low level enable voltage v eh single 0.8 v input forward voltage v f 1.4 1.5 1.75 v t a = 25 c, i f = 10 ma 5 1.3 1.8 v if=10ma input reverse breakdown voltage bv r 5vi r = 10 a 1 input diode temperature coe?cient v f /t a -1.6 mv/c i f = 10 ma 1 input capacitance c in 60 pf f = 1 mhz, v f = 0 v 1
11 switching speci?cations over recommended operating conditions (t a = C40 c to +85 c, 2.7v v cc 3.6v), i f = 7.5 ma unless otherwise speci?ed. all typicals at t a = 25 c, v cc = 3.3 v. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 90 ns r l = 350 c l = 15 pf 6, 7 1, 6, 15 propagation delay time to low output level t phl 75 ns r l = 350 c l = 15 pf 1, 7, 15 pulse width distortion |t phl C t plh | 25 ns r l = 350 c l = 15 pf 8 9, 15 propagation delay skew t psk 40 ns r l = 350 c l = 15 pf 8, 9, 15 output rise time (10-90%) t r 45 ns r l = 350 c l = 15 pf 1, 15 output fall time (90-10%) t f 20 ns r l = 350 c l = 15 pf 1, 15 propagation delay time of enable from v eh tp v el t elh 45 ns r l = 350 , c l = 15 pf, v el = 0 v, v eh = 3 v 910 propagation delay time of enable from v el to v eh t ehl 30 ns r l = 350 , c l = 15 pf, v el = 0 v, v eh = 3 v 911 switching speci?cations (ac) over recommended operating conditions t a = -40c to 85c, 4.5 vcc 5.5v, i f = 7.5 ma unless otherwise speci?ed. all typicals at v cc = 5 v, t a = 25 c. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 20 48 75 ns t a = 25c, r l = 350 , c l = 15 pf 6,7 1,6,15 100 propagation delay time to low output level t phl 25 50 75 ns t a = 25c, r l = 350 , c l = 15 pf 6, 7 1,7, 15 100 pulse width distortion |t phl - t plh | 3.5 35 ns r l = 350 , c l = 15 pf 8 9, 15 propagation delay skew t psk 40 ns r l = 350 , c l = 15 pf 8,9, 15 output rise time (10%-90%) t r 24 ns r l = 350 , c l = 15 pf 1,15 output fall time (10%-90%) t f 10 ns r l = 350 , c l = 15 pf 1, 15 propagation delay time of enable from v eh to v el t elh 30 ns r l = 350 , c l = 15 pf, v el =0v, v eh =3v 910 propagation delay time of enable from v el to v eh t elh 20 ns r l = 350 , c l = 15 pf, v el =0v, v eh =3v 911
12 parameter sym. device min. typ. units test conditions fig. note output high level common mode transient immunity |cm h | hcpl-263l hcpl-063l hcpl-260l hcpl-060l 15 25 kv/ sv cc = 3.3 v, i f = 0 ma, v o(min) = 2 v, r l = 350 , t a = 25c, v cm = 1000 v and v cm = 10v 10 12, 14, 15 output low level common mode transient immunity |cm l | hcpl-263l hcpl-063l hcpl-260l hcpl-060l 15 25 kv/ sv cc = 3.3 v, i f = 7.5 ma, v o(max) = 0.8 v, r l = 350 , t a = 25c, v cm = 1000 v and v cm = 10v 10 13, 14, 15 output high level common mode transient immunity |cm h | hcpl-263l hcpl-063l hcpl-260l hcpl-060l 10 15 kv/ sv cc = 5 v, i f = 0 ma, v o(min) = 2 v, r l = 350 , t a = 25c, v cm = 1000 v 10 12, 14, 15 output low level common mode transient immunity |cm l | hcpl-263l hcpl-063l hcpl-260l hcpl-060l 10 15 kv/ sv cc = 5 v, i f = 7.5 ma, v o(max) = 0.8 v, r l = 350 , t a = 25c, v cm = 1000 v 10 13, 14, 15
13 *the jedec registration speci?es 0?c to +70?c. avago speci?es C40?c to +85?c. **the input-output momentary withstand voltage is a dielectric v oltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-2 insulation characteristics table (if app licable), your equip- ment level safety speci?cation or avago application note 1074 entitled "optocoupler input-output endurance voltage." notes: 1. each channel. 2. peaking circuits may produce transient input currents up to 50 ma, 50 ns maximum pulse width, provided average current does not exceed 20 ma. 3. peaking circuits may produce transient input currents up to 50 ma, 50 ns maximum pulse width, provided average current does not exceed 15 ma. 4. derate linearly above +80?c free-air temperature at a rate of 2.7 mw/?c for the soic-8 package. 5. bypassing of the power supply line is required, with a 0.1 f ceramic disc capacitor adjacent to each optocoupler as illust rated in figure 11. total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 6. the t plh propagation delay is measured from the 3.75 ma point on the falling edge of the input pulse to the 1.5 v point on the rising e dge of the output pulse. 7. the t phl propagation delay is measured from the 3.75 ma point on the rising edge of the input pulse to the 1.5 v point on the falling e dge of the output pulse. 8. t psk is equal to the worst case di?erence in t phl and/or t plh that will be seen between units at any given temperature and speci?ed test conditions. 9. see test circuit for measurement details. 10. the t elh enable propagation delay is measured from the 1.5 v point on the falling edge of the enable input pulse to the 1.5 v point on the rising edge of the output pulse. 11. the t elh enable propagation delay is measured from the 1.5 v point on the rising edge of the enable input pulse to the 1.5 v point on t he falling edge of the output pulse. 12. cm h is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state (i.e., v o > 2.0 v). 13. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., v o < 0.8 v). 14. for sinusoidal voltages, (|dv cm | / dt) max = f cm v cm (p-p). 15. no external pull up is required for a high logic state on the enable input. if the v e pin is not used, tying v e to v cc will result in improved cmr performance. for single channel products only. see application information provided. 16. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 17. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for one s econd (leakage detection current limit, i i-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in the iec/en/din en 60747-5-2 insulation characteristics table, if applicable. 18. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 v rms for one s econd (leakage detection current limit, i i-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in the iec/en/din en 60747-5-2 insulation characteristics table, if applicable. 19. measured between the led anode and cathode shorted together and pins 5 through 8 shorted together. for dual channel produc ts only. 20. measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. for dual channel products only. package characteristics all typicals at t a = 25?c. parameter sym. package min. typ. max units test conditions fig. note input-output i i-o * single 8-pin dip 1 a 45% rh, t = 5 s, 16, 17 insulation single so-8 v i-o = 3 kv dc, t a = 25?c input-output v iso 8-pin dip, so-8 3750 v rms rh 50%, t = 1 min, 16, 17 momentary t a = 25?c withstand voltage** input-output r i-o 8-pin, so-8 10 12 v i-o =500 v dc 1, 16, 19 resistance input-output c i-o 8-pin dip, so-8 0.6 pf f = 1 mhz, t a = 25?c 1, 16, 19 capacitance input-input i i-i dual channel 0.005 a rh 45%, t = 5 s, 20 insulation v i-i = 500 v leakage current resistance r i-i dual channel 10 11 20 (input-input) capacitance c i-i dual 8-pin dip 0.03 pg f = 1 mhz 20 (input-input) dual so-8 0.25
14 figure 1. typical high level output current vs. temperature. figure 3. typical low level output voltage vs. temperature. i oh C high level output current C a -60 0 t a C temperature C c 100 10 15 -20 5 20 v cc = 3.3 v v o = 3.3 v v e = 2.0 v* i f = 250 a 60 -40 0 40 80 * for single channel products only v cc = 3.3 v v o = 0.6 v 12 6 -60 -20 20 60 100 t a C temperature C c 4 80 40 0 -40 0 i th C input threshold current C ma r l = 350 k 2 8 10 r l = 1 k r l = 4 k 8-pin dip, so-8 0.8 0.4 -60 -20 20 60 100 t a C temperature C c 0.2 80 40 0 -40 0 v ol C low level output voltage C v i o = 13 ma 0.1 0.5 0.7 8-pin dip, so-8 v cc = 3.3 v v e = 2.0 v* i f = 5.0 ma 0.3 0.6 * for single channel products only figure 2. typical output voltage vs. forward input current. v cc = 5.0 v v o = 0.6 v 6 3 -60 -20 20 60 100 t a C temperature C c 2 80 40 0 -40 0 i th C input threshold current C ma r l = 350 1 4 5 r l = 1 k r l = 4 k 8-pin dip, so-8 0.8 0.4 -60 -20 20 60 100 t a C temperature C c 0.2 80 40 0 -40 0 v ol C low level output voltage C v i o = 16 ma 0.1 0.5 0.7 i o = 6.4 ma 8-pin dip, so-8 v cc = 5.5 v v e = 2.0 v* i f = 5.0 ma 0.3 0.6 i o = 12.8 ma i o = 9.6 ma * for single channel products only i oh C high level output current C a -60 0 t a C temperature C c 100 10 15 -20 5 20 v cc = 5.5 v v o = 5.5 v v e = 2.0 v* i f = 250 a 60 -40 0 40 80 * for single channel products only
15 figure 6. test circuit for t phl and t plh . figure 5. typical input diode forward characteristic. v cc = 3.3 v v e = 2.0 v* v ol = 0.6 v 70 60 -60 -20 20 60 100 t a C temperature C c 50 80 40 0 -40 20 i ol C low level output current C ma 40 i f = 5.0 ma * for single channel products only i f C forward current C ma 1.1 0.001 v f C forward voltage C v 1.0 1000 1.3 0.01 1.5 1.2 1.4 0.1 t a = 25 c 10 100 8-pin dip, so-8 i f + C v f 1.6 output v o monitoring node 3.3v or 5v 7 5 6 8 2 3 4 1 pulse gen. z = 50 t = t = 5 ns o f i f r l r m v cc 0.1 f bypass *c l gnd input monitoring node r single channel output v o monitoring node 3.3v or 5v 7 5 6 8 2 3 4 1 pulse gen. z o = 50 t f = t r = 5 ns i f r l r m v cc 0.1 f bypass c l * gnd input monitoring node dual channel *c l is approximately 15 pf which includes probe and stray wiring capacitance. 1.5 v t phl t plh i f input v o output i f = 7.50 ma i f = 3.75 ma figure 4. typical low level output current vs. temperature. v cc = 5.0 v v e = 2.0 v* v ol = 0.6 v 70 60 -60 -20 20 60 100 t a C temperature C c 50 80 40 0 -40 20 i ol C low level output current C ma 40 i f = 10-15 ma i f = 5.0 ma * for single channel products only
16 figure 7. typical propagation delay vs. temperature. figure8. typical pulse width distortion vs. temperature. v cc = 3.3 v i f = 7.5 ma 150 120 -60 -20 20 60 100 t a C temperature C c 90 80 40 0 -40 0 t p C propagation delay C ns 60 30 t phl , r l = 350 t plh , r l = 350 v cc = 3.3 v i f = 7.5 ma 50 40 -20 20 60 100 t a C temperature C c 30 80 40 0 -40 pwd C pulse width distortion C ns 20 r l = 350 10 -60 0 v cc = 5.0 v i f = 7.5 ma 100 80 -60 -20 20 60 100 t a - temperature - ?c 60 80 40 0 -40 0 t p - propagation delay - ns 40 20 t plh , r l = 4 k t plh , r l = 1 k t plh , r l = 350 t phl , r l = 350 1 k 4 k v cc = 5.0 v i f = 7.5 ma 40 30 -20 20 60 100 t a - temperature - o c 20 80 40 0 -40 pwd - pulse width distortion - ns 10 r l = 350 r l = 1 k r l = 4 k 0 -60 -10
17 figure 10. test circuit for common mode transient immunity and typical waveforms. figure 11. recommended printed circuit board layout. gnd bus (back) v cc bus (front) enable 0.1f 10 mm max. (see note 5) output nc nc single channel device illustrated. figure 9. test circuit for t ehl and t elh . output v o monitoring node 1.5 v t ehl t elh v e input v o output 3.0 v 1.5 v 3.3v or 5v 7 5 6 8 2 3 4 1 pulse gen. z o = 50 t f = t r = 5 ns i f r l v cc 0.1 f bypass *c l *c l is approximately 15 pf which includes probe and stray wiring capacitance. gnd 7.5 ma input v e monitoring node 3.3v or 5v 7 5 6 8 2 3 4 1 v cc 0.1 f bypass gnd output v o monitoring node pulse generator z o = 50 + i f b a v ff v cm C r l single channel 3.3v or 5v 7 5 6 8 2 3 4 1 v cc 0.1 f bypass gnd output v o monitoring node pulse generator z o = 50 + i f b a v ff v cm C r l dual channel v o 0.5 v v o (min.) 5 v 0 v switch at a: i f = 0 ma switch at b: i f = 7.5 ma v cm cm h cm l v o (max.) v cm (peak) v o
18 figure 12. recommended lvttl interface circuit. *diode d1 (1n916 or equivalent) is not required for units with open collector output. v cc1 3.3 v or 5v gnd 1 d1* i f v f shield single channel device 8 6 5 r l 0.1 f bypass 2 3 + C 3.3 v or 5v gnd 2 v cc2 2 220 1 7 v e v cc1 3.3 v or 5v gnd 1 d1* shield dual channel device channel 1 shown 8 7 5 r l 0.1 f bypass 1 2 + C 3.3 v or 5v gnd 2 v cc2 2 220 1 i f v f
19 figure 13. recommended drive circuit for high-cmr. application information common-mode rejection for hcpl-260l families: figure 13 shows the recom mended drive circuit for op- timal common-mode rejection performance. two main points to note are: 1. the enable pin is tied to v cc rather than ?oating (this applies to single-channel parts only). 2. two led-current setting resistors are used instead of one. this is to balance i led variation during common- mode transients. if the enable pin is left ?oating, it is possible for common- mode transients to couple to the enable pin, resulting in common-mode failure. this failure mechanism only oc- curs when the led is on and the output is in the low state. it is identi?ed as occurring when the transient out- put voltage rises above 0.8 v. therefore, the enable pin should be connected to either v cc or logic-level high for best common-mode performance with the output low (cmr l ). this failure mechanism is only present in single- channel parts which have the enable function. figure 14. ac equivalent circuit. 350 1/2 r led v cc + 15 pf + v cm 8 7 6 1 3 shield 5 2 4 c la v o gnd 0.01 f 1/2 r led c lc i ln i lp C also, common-mode transients can capacitively cou- ple from the led anode (or cathode) to the output-side ground causing current to be shunted away from the led (which can be bad if the led is on) or conversely cause current to be injected into the led (bad if the led is meant to be o? ). figure 14 shows the parasitic capaci- tances which exists between led anode/cathode and output ground (c la and c lc ). also shown in figure 14 on the input side is an ac-equivalent circuit. for transients occurring when the led is on, common- mode rejec tion (cmr l , since the output is in the low state) depends upon the amount of led current drive (i f ). for conditions where i f is close to the switching threshold (i th ), cmr l also depends on the extent which i lp and i ln balance each other. in other words, any condi- tion where common-mode transients cause a momen- tary decrease in i f will cause common-mode failure for transients which are fast enough. 0.01 f 350 74ls04 or any totem-pole output logic gate v o v cc+ 8 7 6 1 3 shield 5 2 4 hcpl-260l gnd gnd2 220 v cc 220 * * * higher cmr may be obtainable by connecting pins 1, 4 to input ground (gnd1). gnd1
for product i nf ormatio n a n d a complete list o f distributors, please go to our website: www.avagotech.com a v ago, a v ago tech n ologies, a n d the a logo are trademarks o f a v ago tech n ologies i n the u n ited states a n d other cou n tries. data subject to cha n ge. cop y right ? 2005 - 2010 a v ago tech n ologies. all rights reser v ed. obsoletes av01 - 0581en av02 - 0 6 1 6 en - februar y 8, 2010 likewise for common-mode transients which occur when the led is o? (i.e. cmr h , since the output is high), if an imbalance between i lp and i ln results in a transient i f equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below 2 v (which consti tutes a cmr h failure). by using the recommended circuit in figure 13, good cmr can be achieved. the balanced i led -setting resistors help equalize i lp and i ln to reduce the amount by which i led is modulated from transient coupling through c la and c lc . cmr with other drive circuits cmr performance with drive circuits other than that shown in figure 13 may be enhanced by following these guidelines: 1. use of drive circuits where current is shunted from the led in the led o? state (as shown in figures 15 and 16). this is bene?cial for good cmr h . 2. use of i fh > 3.5 ma. this is good for high cmr l . figure 15 shows a circuit which can be used with any totem-pole-output ttl/lsttl/hcmos logic gate. the bu?er pnp transistor allows the circuit to be used with logic devices which have low current-sinking capability. it also helps maintain the driving-gate power-supply cur- rent at a constant level to minimize ground shifting for other devices connected to the input-supply ground. when using an open-collector ttl or open-drain cmos logic gate, the circuit in figure 16 may be used. when using a cmos gate to drive the optocoupler, the circuit shown in figure 17 may be used. the diode in parallel with the r led speeds the turn-o? of the optocoupler led. figure 15. ttl interface circuit. figure 16. ttl open-collector/open drain gate drive circuit. figure 17. cmos gate drive circuit. 420 (max) 1 3 2 4 2n3906 (any pnp) v cc 74l504 (any ttl/cmos gate) hcpl-260l led r 1 3 2 4 v cc 74hc00 (or any open-collector/ open-drain logic gate) hcpl-260l led 220 1 3 2 4 v cc 74hc04 (or any totem-pole output logic gate) hcpl-260l 1n4148 led

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